FIG. 5 shows a general structure of a semiconductor memory testing apparatus. The semiconductor memory testing apparatus is comprised of a timing generator 1, a test pattern generator 2, a waveform shaper 3, a logic comparator 4 and a failure analysis memory 5, to examine whether a memory under test (hereinafter referred to as "MUT") works correctly or not.
The test pattern generator 2, which is provided with a reference clock CK that the timing generator 1 generates, outputs an address signal ADRS, a test pattern data signal TPD and a control signal CS to be supplied to the MUT. These signals are first applied to the waveform shaper 3 wherein they are wave-shaped into required waveforms to be sent to the MUT. The control signal CS is used for read/write control of the test pattern data TPD for the MUT.
The read-out data from the MUT which is the result of the test pattern data TPD is applied to the logic comparator 4 and then compared with expected data E output from the pattern generator 2 to examine whether a match has occurred between the read-out data and the expected data or not. Namely, the comparator 4 determines whether the MUT passes or fails a test. If disagreement occurs in the test result, a failure signal FS is supplied to the failure analysis memory 5 by the logic comparator 4. Failure data FD is stored in a memory cell of the failure analysis memory 5 specified by an address signal ADRS output from the test pattern generator 2 by the timing of the fail signal from the logic comparator 4. After the test has been completed, the contents stored in the failure analysis memory 5 are analyzed.
FIG. 6 shows an internal configuration of the failure analysis memory 5. This failure analysis memory 5 is mainly comprised of an address selecting part 51, a memory control part 52 and a memory part 53.
The address selecting part 51 has a function of selecting a part of the address signal ADRS generated by the test pattern generator 2. A higher address selected by the address selecting part 51 is applied to the memory control part 52 and a lower address selected by the address selecting part 51 is applied to each memory unit which forms the memory part 53.
The memory part 53 consists of several blocks each of which is formed of, for example, a 18-bit memory and stores therein the failure data FD corresponding to each address of the MUT or each MUT among the plurality of MUTs under the memory testing. With reference to FIG. 7, the following description explains how to store the failure data FD into the failure analysis memory 5 in the memory testing apparatus. If a certain address of the MUT fails in the memory test, a failure signal FS makes the failure analysis memory 5 store and hold "1" at the address corresponding to the failure address of the MUT by controlling a WE (write enable) or CS (control signal) terminal of the failure analysis memory 5. FIG. 7a shows an example of circuit configuration for storing the fail data through the WE terminal while FIG. 7b shows a configuration for storing the fail data through the control of the CS terminal.
The memory control part 52 consists of an address decoding part, a failure formatting part and a read data formatting part. The address decoding part decodes a higher address than that of the memory unit forming the memory part 53 and outputs a signal for selecting memory unit according to the number of bits in the MUT and also according to the number of MUTs which are under a simultaneous and parallel test by the memory testing apparatus.
The read data formatting part is for the failure analysis after taking the failure data in the memory section 53. The read data formatting part outputs a signal to select the failure data FD to be output from the memory section 53 according to the number of bits in the MUT and also according to the number of MUTs which are under the simultaneous and parallel test by the memory testing apparatus. The failure formatting part selects a failure signal output from the logic comparator corresponding to each test pin of the MUT, according to whether the number of bits in the MUT and the number of MUTs in the test is single or plural, and applies the selected failure signal to the memory part 53. Further, the logical product (AND) of the selection signal output from the address decoding part and the failure signal selected in the failure formatting part is applied to the memory part 53 as a failure signal.
The following description explains a procedure for testing a flash memory by writing a program and evaluating the program with reference to FIG. 8. As is well known in the art, the flash memory is used as an erasable read only memory (ROM). In the use of the flash memory, the writing data in the memory is usually called the "program" as above. The flash memory test is performed as follows.
After writing data in each address of the MUT (flash memory), or equivalently, after the programming, it is verified that the data is written correctly for each address. In this programming process, a programming pulse is also applied to the MUT each time the data is written in the specific address for activating the MUT. If the program (data) was not successfully written in the address within a cycle, the program-writing is repeated until the data is correctly written therein. If the program is written at the last address of the flash memory, the programming test is completed.
Next, an erasing test will be described. All the data in the flash memory is set to "0" in the erasing operation, i.e., the data "0" is written in all the addresses of the MUT. The difference between the erasing operation and a programming operation is an area where data is written. Under the erasing operation, data is written into each block of the MUT. Here, a block means a group of plural addresses. The erasing operation is available in two ways: an operation for erasing the whole memory at once and an operation for erasing one block of memory at a time.
After erasing the whole MUT or each block of the MUT, the first address of the area (whole memory or block) where the erasing operation has been executed is specified for verification and a pass/failure signal output from the logic comparator 4 is recognized. If the pass signal is output, the test is proceeded to the subsequent address in the area wherein the data in the address is compared with the expected data "0". If the subsequent addresses passes, the third address is specified and compared. In this way, the verification of the erase operation is continued to the last address of the area where the erasing operation was executed unless there is a fail in the subsequent address. If the final address of the area passes, the whole MUT or the block of the MUT is judged to be pass.
In case where the first address fails, the erasing operation is applied again. If the first address passes after the erasing operation applied again, the test proceeds to the subsequent address wherein the data in the address is compared with the expected data "0". On the other hand, if the address fails after the erasing operation applied again, the erasing operation is repeated until the address in question passes. If the erasing operation must be repeated up to the determined time, the whole MUT or the block of the MUT is judged to be failure. This process is applied to any addresses in the area until the last address so that each address is evaluated as to whether the total number of failure in the area for erasing the data exceeds the determined time.
In this procedure of testing the flash memory, it would be convenient for the user if the flash memory testing apparatus is capable of counting and storing the number of times the programming pulse data or erasing pulse data is applied to the flash memory under test. The presently available flash memory testing apparatus, however, does not have such a function of counting and storing the data of the number of programming pulses or erasing pulses applied to the flash memory.